1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using high yielding spectra scatterometry measurements to control semiconductor manufacturing processes, and systems for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, integrated circuit devices are comprised of hundreds or millions of transistors formed above a semiconducting substrate. By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate 11.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14 (gate length), that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
One illustrative process flow for forming the illustrative transistor 10 will now be described. Initially, the shallow trench isolation regions 18 are formed in the substrate 11 by etching trenches 18A into the substrate 11 and, thereafter, filling the trenches 18A with an appropriate insulating material, e.g., silicon dioxide. Next, a gate insulation layer 16 is formed on the surface 15 of the substrate 11 between the trench isolation regions 18. This gate insulation layer 16 may be comprised of a variety of materials, but it is typically comprised of a thermally grown layer of silicon dioxide. Thereafter, the gate electrode 14 for the transistor 10 is formed by forming a layer of gate electrode material, typically polysilicon, above the gate insulation layer 16, and patterning the layer of gate electrode material using known photolithography and etching techniques to thereby define the gate electrode 14. The sidewalls 14A of the gate electrode 14 tend to flare outwardly a very small amount. Of course, millions of such gate electrodes are being formed across the entire surface of the substrate 11 during this patterning process. The source/drain regions 22 and the sidewall spacers 20 are then formed using a variety of known techniques. Additionally, metal silicide regions (not shown) may be formed above the gate electrode 14 and the source/drain regions 18.
After an integrated circuit device is fabricated, it is subjected to several electrical tests to insure its operability and to determine its performance capabilities. The performance capabilities of integrated circuit products, e.g., microprocessors, may vary quite a bit despite great efforts to insure that all of the integrated circuit products are fabricated with the same process steps. For example, the operating frequency of microprocessors may vary over a given range. Many factors, or interrelationships among various factors, may be the cause of such variations, and such causes may be difficult to determine. Variations in the performance level of the integrated circuit devices may be problematic for a variety of reasons. For example, at least in the case of microprocessors, higher performance microprocessors tend to sell for higher prices in the marketplace, while lower performance microprocessors tend to sell for lesser prices. Thus, all other things being equal, a microprocessor manufacturer would like to be able to produce as many high performance microprocessors as possible. Stated another way, an integrated circuit manufacturer would like to be able to consistently and reliably mass produce integrated circuit devices at the very highest performance level the product design and manufacturing equipment will allow.
The present invention is directed to a method and systems that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of using high yielding spectra scatterometry measurements to control semiconductor manufacturing processes, and a system of accomplishing same. In one illustrative embodiment, the method comprises providing a library comprised of at least one target optical characteristic trace of a grating structure comprised of a plurality of gate stacks, the target trace corresponding to a semiconductor device having at least one desired electrical performance characteristic, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate stacks, illuminating at least one grating structure formed above said substrate, measuring light reflected off of the grating structure formed above the substrate to generate an optical characteristic trace for the formed grating structure, and comparing the generated optical characteristic trace to the target trace.
The present invention is also directed to various systems for accomplishing the illustrative methods described herein. In one embodiment, the system is comprised of a scatterometry tool, a process tool and a controller. The scatterometry tool is adapted to make scatterometric measurements of a grating structure comprised of a plurality of gate stacks and generate an optical characteristic trace for the grating structure. The scatterometry tool may be further used to compare the generated optical characteristic trace to a target optical characteristic trace that is determined based upon electrical test data for a semiconductor device. If a deviation exists between the generated trace and the target trace, the controller may then be used to control one or more parameters of one or more processes to be performed on the substrate comprised of the deficient or sub-standard gate stacks.